1. Field of the Invention
The present invention relates to a test-facilitating circuit in a semiconductor device, and more particularly relates to a test-facilitating circuit which uses a built-in self test (referred to as “BIST” hereinafter) circuit.
2. Description of the Background Art
Recently, the development of semiconductor devices having mounted memories is actively underway. Typically, since the number of data lines is large and no control signal and no data signal are directly outputted to the external pin of a semiconductor device, a memory core mounted on the semiconductor device is provided with a test interface circuit (referred to as “TIC” hereinafter) for testing the memory core. In a test state, an ATE (Auto Test Equipment) accesses the memory core through the TIC and the memory is thereby tested.
FIG. 1 is a block diagram showing one example of a semiconductor device having a mounted memory having a memory core including a conventional TIC mounted thereon. A semiconductor device having a mounted memory 101 includes a memory core 103, a logic circuit 104 which controls memory core 103, a TIC 105, a selector 106 which receives an output signal from an ATE 102 and outputs the output signal to one of logic circuit 104 and TIC 105, and which receives output signals from logic circuit 104 and TIC 105, respectively and selectively outputs one of the output signals to ATE 102, and a selector 107 which receives output signals from logic circuit 104 and TIC 105, respectively and selectively outputs one of the output signals to memory core 103.
Since an input/output pin dedicated to testing memory core 103 is not provided outside of semiconductor device having a mounted memory 101, ATE 102 switches over selectors 106 and 107 in response to an MTEST signal and performs a test to memory core 103.
However, even if this TIC is mounted on a semiconductor device, the cost of the semiconductor device is disadvantageously pushed up because of a large number of pins required for the test, a small number of times of measurement for the test, need to use an expensive ATE and the like. Various types of test-facilitating methods have been developed as techniques for solving this disadvantage. Among them, a BIST technique has been particularly introduced to logic circuit loading memories.
Nevertheless, since logic circuit loading memories differ from one another in memory specifications such as the data configuration of a memory core mounted thereon, read latency and data capacity, it is necessary to reconstruct a BIST circuit for each semiconductor device. Since logic circuit loading memories are customized to respective systems, the production volume of logic circuit loading memories differ according to the systems. While it is demanded to develop semiconductor devices in short time, it has been disadvantageously difficult to mount a BIST circuit corresponding to memory cores of various specifications on a semiconductor device.